Cache coherency controller for MESI protocol based on FPGA

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each called a core. The new chips processors multi-core processor. This design makes to work simultanously for job or all cores working parallel same job. All are similar their design, core has its own cache memory, while shares main memory. So if requestes block data from memory cache, there should be protocol declare situation this other cores.This is coherency consistency multi-core. paper special designed very high speed hardware description language (VHDL) coding implemented ISE Xilinx software. used modified, exclusive, shared invalid (MESI) protocol. Test results were taken by test bench, showed states correctly.